Clock frequencies and data transfer rates continue to increase in many microprocessor based devices. In the past, analog phase-locked loop (PLL) circuits were frequently employed for frequency synthesis, clocking, and data transfer. With a growing trend toward smaller, portable microprocessor based devices the relatively high power draw of PLL circuitry proved detrimental. Digitally controlled PLLs provide a generally more robust construction, consumer less power than analog PLLs, and require less real estate on increasingly packed integrated circuits. Within a digitally controlled PLL, a digitally controlled oscillator (DCO) replaces the voltage controlled oscillator (VCO) found in earlier analog PLL systems. Similar to their analog counterpart, changes within the system (e.g., temperature changes, voltage changes, changes in component resistance or impedance, and similar) may cause the output provided by a digitally controlled oscillator to drift over time. To correct such drift, a state machine may provide DCO code updates to tune the output of the DCO based on current system parameters. Typically, these code updates are provided by the state machine without synchronization to the clocking of the DCO itself. Such asynchronous updates may occur at times when the DCO delay chain has different logic states at the switching points, increasing the possibility of transient glitches in the DCO clock output. Such glitches in the DCO clock output may lead to unfavorable system behaviors such as limiting the ability to tune a clock generator during memory operations.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications and variations thereof will be apparent to those skilled in the art.